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China Suppliers Factory: Ka-band Asymmetric Doherty Power Amplifier for High Efficiency & Linear Performance

The **Ka-band Asymmetric Doherty Power Amplifier** stands out as a premier solution for high-efficiency, linear performance in Ka-band communication systems. Designed with an innovative asymmetric Doherty architecture, this amplifier optimally distributes power between the main and auxiliary amplifying paths, resulting in enhanced back-off efficiency ideal for high peak-to-average power ratio (PAPR) signals. With low insertion loss, improved gain, and outstanding thermal stability, it caters perfectly to applications in satellite communications, millimeter-wave 5G/6G links, phased-array transmitters, and high-performance RF front-ends. Manufactured in China, this product ensures superior output power, reduced energy consumption, and reliable long-term operation, making it a top choice among suppliers and factories in the industry. Experience unmatched performance and efficiency, tailored for demanding environments with our advanced Ka-band amplifier

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    Product Overview

    Featuring a compact 0.26 mm² footprint, this 65nm CMOS Doherty PA delivers high efficiency (28.2% PAE) and linearity. Optimized for 35-41 GHz, it is ideal for cost-effective 5G mmWave and satellite phased array applications.

    Parameter Specification
    Process 65nm CMOS
    Operating Frequency (GHz) 35-41
    Gain (dB) @10 GHz 25
    Psat (dBm) @38 GHz 23.3
    OP1dB (dBm) @38 GHz 22.4
    PAEmax (%) @38 GHz 28.2
    Core Area (mm²) 0.26

    Frequently Asked Questions

    What semiconductor process does this Doherty PA use?

    This Doherty Power Amplifier (PA) is fabricated using a standard 65nm CMOS process, making it highly cost-effective for mass production.

    What is the operating frequency range of this device?

    The device is optimized to operate efficiently within the frequency range of 35 GHz to 41 GHz.

    What are the output power and efficiency specifications at 38 GHz?

    At 38 GHz, the Doherty PA delivers a saturated output power (Psat) of 23.3 dBm, an output 1-dB compression point (OP1dB) of 22.4 dBm, and achieves a maximum Power Added Efficiency (PAEmax) of 28.2%.

    How compact is the core area of this chip?

    It features an extremely compact footprint with a core area of only 0.26 mm², enabling easy integration into dense array configurations.

    What are the primary target applications for this CMOS PA?

    Due to its high efficiency, linearity, and compact size, it is ideal for 5G millimeter-wave (mmWave) communications and satellite phased array applications.

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